Parallel data buses are often used to interconnect integrated circuit devices. In a parallel synchronous bus, data is generally supplied onto the bus by a first integrated circuit device for a second integrated circuit device to read. The second device clocks in the data on an edge of a clock signal. Accordingly, the data must be set up and stable on the data input terminals of the second device for a period of time before the edge of the clock signal that causes the second device to clock in the data. Bus specifications generally require that data be stable for some “set up time” before the clock edge that clocks in the data. Bus specifications generally also require that the data remain stable until some “hold time” after the clock edge.
FIG. 1 (Prior Art) illustrates three bus cycles. The data supplied onto the bus in the first cycle is D1, the data supplied onto the bus in the second cycle is D2, and the data supplied onto the bus in the third cycle is D3. The data is clocked into the receiving device on the rising edge of the clock signal CLK. The specifications of the bus require that the data for a bus cycle be set up and stable by the “set up time” TS before the rising edge of the clock, and that the data for the bus cycle remain valid until a “hold time” TH after the rising edge of the clock.
In a synchronous system, the rate or frequency at which data can be sent between two devices that are connected by means of a parallel bus is a function of the clock to output delay of the transmitting device, the setup and hold time of the receiving device, clock jitter, the clock skew between the two devices, the propagation delay associated with the bus, and other physical phenomena that cause timing uncertainty at the receiver. In a source synchronous system, the clock skew between the devices and the propagation delay associated with the bus do not affect the frequency of operation. Physical phenomena like simultaneous switching output (SSO) noise, pattern dependent propagation delay, and crosstalk all cause uncertainty in the timing of the data signals at the input of the receiving device. That is, they affect the position of the data valid window with respect to the clock. This uncertainty in the timing of the data valid window with respect to the clock is, to a large extent, dependent on the data pattern itself.
In some integrated circuit devices, a problem arises when the data being output onto the bus switches in a particular way. When an output buffer switches from driving a digital logic high (“high”) to driving a digital logic low (“low”), the capacitance of the output terminal and external wire attached to it must be discharged through the output buffer in order for the voltage on the output terminal to transition from the higher voltage (“high”) to the lower voltage (“low”). If many output buffers simultaneously switch in this way from outputting a “high” to outputting a “low,” and if all the output buffers share a common ground bus, then a spike of current will be sinked into the ground bus during the period of switching. If the ground bus has an appreciable inductance and if all of the current spike flows through that inductance, then the current spike may cause the instantaneous voltage on the ground bus to rise. This phenomena is called “ground bounce.” Such ground bounce generally reduces the difference between the supply voltage (VDD) and the ground voltage (GND) for the output buffer, thereby reducing the ability of the output buffer to sink current. Reducing the ability of the output buffer to sink current reduces the high-to-low switching speed of the output buffer. If, for example, there is a sixteen bit data bus and all the sixteen bits switch from “high” to “low,” then the sixteen output buffers may be slowed to a significant degree.
While ground bounce may affect a ground bus, a similar condition, referred to as “VDD droop” or “voltage droop,” can affect conductors carrying a supply voltage. If a substantial current is drawn through a conductor providing a supply voltage, for example a substantial transient current incident to switching of semiconductor devices during a logic transition, a significant voltage drop can occur across the conductor providing the supply voltage, thereby effectively lowering the supply voltage. As with ground bounce, voltage droop can also lead to a reduction of the switching speed of logic devices, for example an output buffer. Thus, transitions in signals processed by such logic devices may occur later or more slowly than they otherwise would. The difficulty in finding a satisfactory solution to this problem has been exacerbated by the insidious nature of the problem itself, in that the slowing of transitions can result from current drawn as a consequence of the mere presence of the transitions. Hence, the slowing, delay, or degradation that occurs in the presence of transitions can be referred to generally as transition-induced delay.
The relative effects of ground bounce and voltage droop may vary according to several factors. For example, the sizes and geometries of transistors may affect the susceptibility of a circuit to ground bounce and VDD droop. For example, in a circuit with larger p-channel metal oxide semiconductor (PMOS) transistors, the larger PMOS transistors may carry more current, resulting in less sensitivity to voltage droop. However, such a circuit may still be affected by significant ground bounce. As another example, various parasitics may also affect the relative influence of ground bounce and VDD droop. Such parasitics can include, for example, parasitic capacitances resulting from a conductor being routed in proximity to another conductor or electrical structure. Integrated circuit packaging and pin assignment (e.g., the number of pins assigned to carry signals as compared to the number of pins assigned to carry power, such as a supply voltage or ground).
Circuits exhibiting different relative susceptibilities to ground bounce and VDD droop may exhibit different transition-induced delay characteristics depending on the directions of the transitions. For example, a rising transition and a falling transition may have different effects on the amount of current flowing through the ground bus and the voltage supply conductor.
FIG. 2 (Prior Art) illustrates an example of transition-induced delay. From the second bus cycle to the third bus cycle, many data bits switch, thereby slowing the transition of the data from data value D2 to data value D3. This delay causes a set up time violation in that data value D3 is not stable by the set up time TS before the third rising edge of the clock CLK.
The output register and data buffer circuitry could be designed to output the data earlier with respect to the clock signal CLK to compensate for the slowness of the output buffer, but then a different problem might present itself in a high speed bus design. FIG. 3 (Prior Art) illustrates this situation. If relatively few of the bits on the data bus switch, then no substantial transition-induced delay occurs. Thus, for a bit that does switch, the output buffers may switch so fast that the hold time TH for the prior cycle (in this case, the second bus cycle) will be violated. In the example of FIG. 3, the data value D2 is removed before the required hold time TH from the second rising edge of the clock.
While ground bounce and VDD droop can affect switching speeds and adversely affect timing relationships, similar effects can result from the influence of conductors in close proximity to one another. For example, propagation delay of a signal through a conductor in a heterogeneous environment (e.g., a microstrip line on an integrated circuit (IC) package substrate or printed circuit (PC) board) is dependent on signals on other conductors in close proximity. The nominal propagation delay of a signal through a conductor is a function of the conductor geometry and the material properties of the dielectric materials surrounding the conductor.
However, when signals on neighboring conductors have the same phase as the affected signal (e.g., have simultaneous transitions of polarity similar to that of the affected signal), which may be referred to as an even mode pattern, then the propagation delay of the affected signal is increased. When the signals on the neighboring conductors have phases opposite that of the affected signal (e.g., have simultaneous transitions of polarity opposite that of the affected signal), which may be referred to as an odd mode pattern, then the propagation delay of the affected signal is decreased. Such phenomena result in pattern-dependent delay that can cause timing uncertainty at a receiver of the affected signal. A solution to these problems is desired.